1. Field of the Invention
The present invention relates to a capacitor used in a semiconductor memory device, and more particularly, to a stacked capacitor and a method of fabricating the same.
2. Description of Related Art
As the complexity of Integrated Circuits (ICs) increase, the demand for a capacitor with a small size, yet sufficient capacitance, increases as well. Conventional methods have utilized a stacked capacitor that has a storage node extending upward from the semiconductor substrate. To achieve sufficient capacitance while reducing the area occupied by the capacitor, the height of the storage node of the stacked capacitor is continuously increased.
FIGS. 1A through 1F are cross-sectional views of a semiconductor substrate illustrating a conventional process of forming a stacked capacitor.
As shown in FIG. 1A, a semiconductor substrate 100 with a gate electrode, a bit line, and impurity regions is prepared. An inter-layer insulating layer 110 with a plurality of contact holes 115 penetrating the insulating layer 110 is provided on the semiconductor substrate 100. Each of the contact holes 115 is filled with a contact pad 120 which connects a storage node of a capacitor to be formed in subsequent processes to the impurity regions. An etching stop layer 130, a sacrificial insulation layer 145, and an anti-reflection layer (ARL) 150 are further formed over the inter-layer insulating layer 110 and the contact pads 120. The anti-reflection layer 150 is composed of nitride and the sacrificial insulation layer 145 is composed of a boron phosphorous silicate glass (BPSG) or an oxide deposited by chemical vapor deposition (CVD).
Next, as shown in FIG. 1B, a photoresist film pattern 190 is formed on the antireflection layer 150. Then, the anti-reflection layer 150, the sacrificial insulation layer 145, and the etching stop layer 130 is selectively etched according to the photoresist film pattern 190, thereby forming openings 155 to expose the contact pads 120.
Next, referring to FIG. 1C, the photoresist film pattern 190 is removed using a conventional ashing process. Cleaning processes using solutions containing sulfuric acid (SCl) or hydrofloric acid (HF) are performed to remove polymer. The polymer is a byproduct of the earlier etching process that forms on the inner walls of openings 155. During these cleaning processes, the sacrificial insulation layer 145 and the inter-layer insulation layer 110 is etched at a greater etch rate than the etching stop layer 130.
Next, a first conductive layer 160 is formed on an entire surface of the resultant structure including the inner surface of the openings 155. The first conductive layer 160 will form a portion of the capacitor. Next, a gap-filling CVD process is performed to fill the openings 155 with an insulation layer 165 composed of a material such as high temperature undoped silica glass (USG).
Next, referring to FIG. 1D, a chemical-mechanical polishing process or “etch-back” process is applied to the high temperature USG insulation layer 165 until the sacrificial insulation layer 145 is exposed, thereby forming a plurality of storage nodes 161 by separating the first conductive layer 160 into several components.
Next, referring to FIG. 1E, the sacrificial insulation layer 145 and the insulation layer 165 seen in FIG. 1D are removed by a wet etching process. The etching stop layer 130 prevents the underlying inter-layer insulation layer 110 from being exposed by the wet etching process.
Next, referring to FIG. 1F, a dielectric layer 170 is formed on the entire surface of the resultant structure and then an oxidation process or rapid thermal annealing (RTA) is performed. The dielectric layer is formed of one of the group consisting of NO, ONO, Ta2O5 and Al2O3 Finally, a second conductive layer 175 is formed on the dielectric layer 170, which completes the capacitor structure.
The conventional method shown in FIGS. 1A-1F for forming a capacitor has some drawbacks. For example, in FIG. 1E, when the height h1 of the storage nodes 161 is too great, the storage nodes 161 may crumble during the subsequent cleaning processes because they lack support. Furthermore, when the distance d1 between adjacent storage nodes 161 is too small, the storage nodes may become abutted, whereby a connecting bridge is formed between them.
To avoid these drawbacks, the distance d1 must be constantly maintained everywhere between two adjacent storage nodes 161, and the height of the storage node 161 must be limited to an adequate extent. Accordingly, these considerations limit the complexity of the IC and prevent size reductions of the semiconductor chip. Additionally, when the sacrificial insulation layer 145 is etched to form the openings 155, through holes frequently form in the inter-layer insulation layer 110 due to over-etching.
Over-etching of the sacrificial insulation layer 145 must be avoided. Over-etching makes it difficult to achieve a vertical profile for the openings 155. Without a vertical profile, the surface area inside the openings 155 is reduced and therefore the area of storage node 161 that is conformable to the inner surfaces of the openings 155 is reduced. The reduced area of storage nodes 161 also reduces the capacitance of the capacitor. Therefore, it is very difficult to get enough capacitance and enough contact area between the storage node and the contact pad.